Relative Timing Latch Controller with Significant Improvement on Power, Performance, and Robustness

In this paper, a simplified and fast latch controller for asynchronous micropipeline is designed, which can be commonly employed in emerging neuromorphic computers. The natural timing relationship of control signals is concerned to reduce the complexity, and timing assumption is used as an extra dimension to improve the performance. A comprehensive comparative investigation is carried out between the new designed latch controller and existing counterparts. The comparison results show that the design method may lead to 2+times improvements over existing methods on performance, power and robustness.