采用TCNCP技术开发大模小间距倒装芯片BGA

Yanggyoo Jung, Minjae Lee, Sunwoo Park, Do-Hyun Ryu, Youshin Jung, Chanha Hwang, Choonheung Lee, Sungsoon Park, M. Jimarez, Myung-June Lee
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引用次数: 21

摘要

最近,与细间距倒装芯片或FPFC相关的技术在各种下一代设备中取得了巨大成就,可以显着增加信号I/O数量并实现低尺寸封装。因此,采用小尺寸芯片、封装尺寸小于16×16mm的细间距铜柱倒装芯片芯片规模封装(CSP)已经采用非导电浆料热压缩键合(TCNCP)技术进行了大批量生产[1-2]。以倒装芯片球栅阵列(FCBGA)为例,对铜柱FPFC技术的需求日益增长,以支持下一代硅节点。然而,在传统的质量回流工艺中,由于CTE不匹配引起的低k模具和基板之间的高度关注的拉伸应力,特别是在模具边缘,将有很高的可能性出现良率下降问题和潜在的可靠性。与正常间距(即150um)倒装芯片BGA相比,这可能是细间距器件的关键质量问题。因此,在细间距铜柱倒装芯片BGA上研究TCNCP键合作为替代方案。本文将讨论用于大尺寸倒装芯片BGA的小间距倒装芯片组装技术。对于大型FPFCBGA封装,将比较两种用于倒装芯片键合的组装方法,质量回流键合和热压缩键合。同时,介绍了预加底填工艺的TC粘接的优点。为了在大型FPFCBGA的芯片和基板之间实现坚固的互连,结合测试的结果将通过几种表面处理来描述,例如ENEPIG,直接浸金(DIG),浸锡(IT)和基板上的焊料涂层。有趣的是,其中一种表面处理显示出优异的可靠性测试结果。最后,本文将从装配的角度讨论一种有效的方法。
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Development of large die fine pitch flip chip BGA using TCNCP technology
Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achievements for various next generation devices, allowing a significant increase in the number of signal I/O and achieving low form factor packages. Consequently, fine pitch Cu pillar flip chip Chip Scale Package (CSP) with small sized die, with package dimension of less than 16×16mm, is already under high volume production using the Thermal-Compression Bonding with Non-conductive Paste (TCNCP) technology [1-2]. In the case of Flip Chip Ball Grid Array (FCBGA), there is a growing need for FPFC technology with Cu pillar in supporting next generation silicon node. However, there will be a high possibility of yield drop issue in conventional mass-reflow process and potential reliability due to the highly concerned tensile stress between low k die and substrate by CTE mismatch especially at the edge of the die. This can be a critical quality issue for fine pitch devices compared to normal pitch (i.e., 150um) flip chip BGA. Therefore, TCNCP bonding as an alternative should be studied on fine pitch Cu pillar flip chip BGA. This paper will discuss fine pitch flip chip assembly technology for large sized flip chip BGA. Two kinds of assembly method, mass reflow bonding versus thermal compression bonding, for the flip chip bonding will be compared for the large FPFCBGA package. Meanwhile, the advantage of TC bonding with pre-applied underfill process will be described. For robust interconnection between die and substrate for large FPFCBGA, the result of the bonding test will be described with several surface finishes such as ENEPIG, Direct Immersion Gold (DIG), Immersion Tin (IT), and Solder Coating on substrate. Interestingly, one of selected surface finishes has shown excellent reliability test results. Finally, this paper will discuss an effective approach for fine pitch devices from an assembly perspective.
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