Ching-Sung Wang, Shih-Yi Yuan, Ke-Horng Chen, S. Kuo
{"title":"一种用于低内压ULSI系统的新型BiCMOS增加全摆幅变换器","authors":"Ching-Sung Wang, Shih-Yi Yuan, Ke-Horng Chen, S. Kuo","doi":"10.1109/ISCAS.1997.621510","DOIUrl":null,"url":null,"abstract":"In this paper a new BiCMOS increased full swing inverter (IFSI) and a new BiCMOS increased full swing buffer (IFSB) for low voltage/low power ULSI (Ultra Large Scale Integration) systems are proposed. These circuits can operate at low internal voltage (V/sub int/) and have low input signal swing. As long as V/sub int/>|V/sub t/| (assuming V/sub tn/=-V/sub tp/), the circuits can work properly. The proposed BiCMOS IFSC circuits are suitable for high-speed operations. When the capacitor load is larger than 0.6 pf; the propagation delay and the delay power product at different internal voltages are better than previous circuits under the same circuit design parameters. We also establish the relationship between the Kr=Kn/Kp ratio and the circuit area. This can avoid the trial and error step in the circuit sizing operation to reduce the power consumption.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"10 21 1","pages":"1856-1859 vol.3"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A new BiCMOS increased full swing converter for low-internal-voltage ULSI systems\",\"authors\":\"Ching-Sung Wang, Shih-Yi Yuan, Ke-Horng Chen, S. Kuo\",\"doi\":\"10.1109/ISCAS.1997.621510\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a new BiCMOS increased full swing inverter (IFSI) and a new BiCMOS increased full swing buffer (IFSB) for low voltage/low power ULSI (Ultra Large Scale Integration) systems are proposed. These circuits can operate at low internal voltage (V/sub int/) and have low input signal swing. As long as V/sub int/>|V/sub t/| (assuming V/sub tn/=-V/sub tp/), the circuits can work properly. The proposed BiCMOS IFSC circuits are suitable for high-speed operations. When the capacitor load is larger than 0.6 pf; the propagation delay and the delay power product at different internal voltages are better than previous circuits under the same circuit design parameters. We also establish the relationship between the Kr=Kn/Kp ratio and the circuit area. This can avoid the trial and error step in the circuit sizing operation to reduce the power consumption.\",\"PeriodicalId\":68559,\"journal\":{\"name\":\"电路与系统学报\",\"volume\":\"10 21 1\",\"pages\":\"1856-1859 vol.3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"电路与系统学报\",\"FirstCategoryId\":\"1093\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.1997.621510\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"电路与系统学报","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.1109/ISCAS.1997.621510","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new BiCMOS increased full swing converter for low-internal-voltage ULSI systems
In this paper a new BiCMOS increased full swing inverter (IFSI) and a new BiCMOS increased full swing buffer (IFSB) for low voltage/low power ULSI (Ultra Large Scale Integration) systems are proposed. These circuits can operate at low internal voltage (V/sub int/) and have low input signal swing. As long as V/sub int/>|V/sub t/| (assuming V/sub tn/=-V/sub tp/), the circuits can work properly. The proposed BiCMOS IFSC circuits are suitable for high-speed operations. When the capacitor load is larger than 0.6 pf; the propagation delay and the delay power product at different internal voltages are better than previous circuits under the same circuit design parameters. We also establish the relationship between the Kr=Kn/Kp ratio and the circuit area. This can avoid the trial and error step in the circuit sizing operation to reduce the power consumption.