带开关rc带隙基准的14.8μVRMS集成无噪声输出电容低压差稳压器

Raveesh Magod, Naveen Suda, V. Ivanov, Ravi Balasingam, B. Bakkaloglu
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引用次数: 4

摘要

实现低噪声正成为射频和混合信号SoC应用的线性电源稳压器的重要要求。提出了一种采用开关rc带隙基准和多回路无条件稳定误差放大器的低噪声、低差稳压器,用于无输出电容的工作。采用开关rc采样保持滤波带隙参考放大器和电流模式斩波误差放大器技术来降低LDO的输出噪声。开关电容陷波滤波器用于保证无斩波纹波输出电压。所提出的技术将LDO的10Hz ~ 100kHz综合输出噪声从95.3 μ vrms降低到14.8μVrms。LDO最大负载电流为100mA,压降电压为230mV,静态电流消耗为40μA。它在10kHz时实现50dB的PSR,可编程输出电压范围为1V-3.3V。采用0.25μm CMOS工艺制造,LDO核心面积为0.18mm2。
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A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference
Achieving low noise is becoming an important requirement in linear supply regulators for RF and mixed-signal SoC applications. A low-noise, low dropout regulator using switched-RC bandgap reference and a multi-loop, unconditionally stable error amplifier for output capacitor-less operation is presented. Switched-RC sample-and-hold filtered bandgap reference and current-mode chopped error amplifier techniques are used for reducing output noise of the LDO. A switched capacitor notch filter is used to ensure chopping ripple free output voltage. The proposed techniques reduce the 10Hz to 100kHz integrated output noise of the LDO from 95.3uVrms to 14.8μVrms. The LDO delivers a maximum load current of 100mA with a dropout voltage of 230mV and quiescent current consumption of 40μA. It achieves a PSR of 50dB at 10kHz for programmable output voltage range of 1V-3.3V. Fabricated in a 0.25μm CMOS process, the LDO core occupies an area of 0.18mm2.
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