Performance Improvement of Radix-4 Booth Multiplier on Negative Partial Products

The traditional Booth decoding applied in Radix-4 Booth multiplier algorithm, introduces a lot of complement operations during processing negative partial products, which increases the design complexity and deteriorates the system performance. To handle this issue, combinations of the classification partial products are analyzed to eliminate the complement conversion in certain situations. Based on this algorithm, an improved 16X16 Radix-4 Booth multiplier with a novel two-stage decoding process is proposed. The design is implemented with Synopsys Design Compiler under SMIC CMOS 55nm technology. The synthesis results show that this work has improvement on reducing the power consumption, boosting the working speed, and narrowing the circuit size.