POWER7TM本地时钟和时钟存储元件

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI:10.1109/ISSCC.2010.5433995

J. Warnock, L. Sigal, D. Wendel, K. Muller, J. Friedrich, V. Zyuban, E. Cannon, A. KleinOsowski

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引用次数: 26

摘要

时钟存储元件(cse)和相关本地时钟电路的设计是现代微处理器项目的关键考虑因素[1]，采用45nm绝缘体上硅(SOI)技术设计的POWER7™芯片[2]也不例外。数字逻辑包含超过2M个cse，这些元件的设计不仅对芯片的面积、功率和性能有重大影响，而且对可靠性、可测试性以及调试和优化硬件的能力也有重大影响。本文将重点讨论添加到CSE设计中的特殊功能，并牢记这些注意事项。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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POWER7TM local clocking and clocked storage elements

The design of the clocked storage elements (CSEs) and associated local clocking circuitry is a critical consideration for modern microprocessor projects[1], and the POWER7™ chip[2], designed in a 45nm silicon-on-insulator (SOI) technology, was no exception. The digital logic contained over 2M CSEs, and the design of these elements had a major impact not only on the area, power, and performance of the chip, but also on the reliability, testability, and the ability to debug and optimize the hardware. This paper will focus on the special features added to the CSE design with these considerations in mind.

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2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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