稳健的TiN HM工艺克服了14nm节点SAV方案的腐蚀问题

Tzu-Hao Fu, Y. Ke, Shi-Chun Tsai, Chun-Ling Lin, Kuo-Wei Chen, M. Huang, Gary Cho, San-Fu Lin, Ting-Jun Wang, A. Cheng
{"title":"稳健的TiN HM工艺克服了14nm节点SAV方案的腐蚀问题","authors":"Tzu-Hao Fu, Y. Ke, Shi-Chun Tsai, Chun-Ling Lin, Kuo-Wei Chen, M. Huang, Gary Cho, San-Fu Lin, Ting-Jun Wang, A. Cheng","doi":"10.1109/IITC-MAM.2015.7325602","DOIUrl":null,"url":null,"abstract":"For advance node such as 14nm technology and beyond, back end of line interconnect has implemented self-aligned via (SAV) schemes for better via-metal short process window [1]. A TiN metal hard mask (MHM) is used for the trench pattern definition, after which via lithography and partial via (PV) etch is performed where the TiN was opened. The via etch condition has very good selectivity so that via is formed in a self-aligned fashion by TiN HM [2]. It is indeed to have significant benefit of via to metal short [3]. However, one of the trade off in SAV scheme is the via under etch that whether or not via can well land on an opened oxide area during PV etch. To define the contact area between via resist hole and opened HM oxide as an effective area for via to open successfully. “Fig. 1” shows the effective area change during process variation due to Via alignment, Via photo resist CD variation (Via ADICD) and post hard mask etch CD variation (AMICD). “Fig. 2” shows the mechanism of this under etch failure mode and typical TEM image from 64nm metal pitch test vehicle. In this work, we try to enlarge the process window by an aggressive AMICD targeting in combining with a higher density TiN material to maintain profile.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"60 9 1","pages":"13-16"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Robust TiN HM process to overcome under etch issue for SAV scheme on 14nm node\",\"authors\":\"Tzu-Hao Fu, Y. Ke, Shi-Chun Tsai, Chun-Ling Lin, Kuo-Wei Chen, M. Huang, Gary Cho, San-Fu Lin, Ting-Jun Wang, A. Cheng\",\"doi\":\"10.1109/IITC-MAM.2015.7325602\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For advance node such as 14nm technology and beyond, back end of line interconnect has implemented self-aligned via (SAV) schemes for better via-metal short process window [1]. A TiN metal hard mask (MHM) is used for the trench pattern definition, after which via lithography and partial via (PV) etch is performed where the TiN was opened. The via etch condition has very good selectivity so that via is formed in a self-aligned fashion by TiN HM [2]. It is indeed to have significant benefit of via to metal short [3]. However, one of the trade off in SAV scheme is the via under etch that whether or not via can well land on an opened oxide area during PV etch. To define the contact area between via resist hole and opened HM oxide as an effective area for via to open successfully. “Fig. 1” shows the effective area change during process variation due to Via alignment, Via photo resist CD variation (Via ADICD) and post hard mask etch CD variation (AMICD). “Fig. 2” shows the mechanism of this under etch failure mode and typical TEM image from 64nm metal pitch test vehicle. In this work, we try to enlarge the process window by an aggressive AMICD targeting in combining with a higher density TiN material to maintain profile.\",\"PeriodicalId\":6514,\"journal\":{\"name\":\"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)\",\"volume\":\"60 9 1\",\"pages\":\"13-16\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC-MAM.2015.7325602\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC-MAM.2015.7325602","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

对于先进的节点,如14nm及以上的技术,后端线互连已经实现了自对准通孔(SAV)方案,以获得更好的通孔金属短工艺窗口[1]。TiN金属硬掩膜(MHM)用于沟槽图案定义,然后通过光刻和部分通孔(PV)蚀刻在TiN打开的地方进行。通过蚀刻条件具有很好的选择性,使得通过形成自对准方式的TiN HM[2]。确实是通过对金属短[3]有显著的好处。然而,SAV方案中的一个权衡是蚀刻下的通孔,在PV蚀刻期间,通孔是否能很好地落在开放的氧化区。确定通孔电阻孔与打开的HM氧化物之间的接触面积,作为通孔成功打开的有效面积。“图1”显示了在工艺变化过程中由于Via对准、Via光抗蚀CD变化(Via ADICD)和后硬掩模蚀刻CD变化(AMICD)而导致的有效面积变化。如图2所示为腐蚀失效模式下的机理,以及64nm金属间距测试车的典型TEM图像。在这项工作中,我们试图通过积极的AMICD瞄准结合更高密度的TiN材料来扩大工艺窗口,以保持轮廓。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Robust TiN HM process to overcome under etch issue for SAV scheme on 14nm node
For advance node such as 14nm technology and beyond, back end of line interconnect has implemented self-aligned via (SAV) schemes for better via-metal short process window [1]. A TiN metal hard mask (MHM) is used for the trench pattern definition, after which via lithography and partial via (PV) etch is performed where the TiN was opened. The via etch condition has very good selectivity so that via is formed in a self-aligned fashion by TiN HM [2]. It is indeed to have significant benefit of via to metal short [3]. However, one of the trade off in SAV scheme is the via under etch that whether or not via can well land on an opened oxide area during PV etch. To define the contact area between via resist hole and opened HM oxide as an effective area for via to open successfully. “Fig. 1” shows the effective area change during process variation due to Via alignment, Via photo resist CD variation (Via ADICD) and post hard mask etch CD variation (AMICD). “Fig. 2” shows the mechanism of this under etch failure mode and typical TEM image from 64nm metal pitch test vehicle. In this work, we try to enlarge the process window by an aggressive AMICD targeting in combining with a higher density TiN material to maintain profile.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
High-voltage monolithic 3D capacitors based on through-silicon-via technology Wafer level metallic bonding: Voiding mechanisms in copper layers A flexible top metal structure to improve ultra low-k reliability Nanostructured material formation for beyond Si devices Ni silicides formation: Use of Ge and Pt to study the diffusing species, lateral growth and relaxation mechanisms
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1