一个1Mb的28nm STT-MRAM,在1.2V VDD下,使用单帽偏移抵消感测放大器和原位自写终止,读取访问时间为2.8ns

Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Y. Shih, Y. Chih, T. Chang, D. Blaauw, D. Sylvester
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引用次数: 59

摘要

1T1R自旋-传递-扭矩(STT) MRAM是下一代高密度嵌入式非易失性存储器的有希望的候选材料[1-2]。然而,1T1R STT-MRAM的传感裕度有限,写入功率高。如图30.2.1(a)所示,由于高阻状态(RAP)和低阻状态(RP)之间的差异很小(仅为2x),以及RAP随温度升高而退化,感测放大器的设计具有挑战性。此外,RP和RAP阻力分布随工艺变化而变化,需要一个跟踪工艺的读参考(Vref)。为了提高感知余量,已经报道了几种偏移抵消方法来减少感知放大器失配[3]。然而,这些方法使用多个电容器,因此产生显著的面积开销。为了解决这个问题,我们提出了一种偏移抵消感测放大器,它只使用一个电容,可以显着提高60%以上的感测裕度。STT-MRAM的第二个设计挑战源于在写入操作期间翻转电池所需的高电流。对于需要10年保持时间的非易失性存储器应用,写入电流可高达几百μA。但是,如图30.2.1(b)所示,所需写入时间随所需状态变化(0→1或1→0)、工艺变化和温度而变化。因此,固定的写时间可以确保在所有条件下都能成功写入,这会在典型或平均条件下浪费大量的能量。在大多数情况下,我们提出了一种就地写自终止方法来减少写能量。感测放大器被重新配置为连续监视写操作,并在检测到状态转换时自动关闭写驱动器,而没有面积或时间损失。此外,在每个数组中添加双虚拟列,以提供逐行PVT变化的读Vref跟踪。采用28nm工艺制备了1Mb STT-MRAM,在25°C和120°C下分别实现了2.8ns和3.6ns的读取访问时间。采用原位自写终止技术,在25°C条件下,写入功率降低47%,写入存取时间为20ns,在120°C条件下,写入功率降低60%。
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A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination
1T1R spin-transfer-torque (STT) MRAM is a promising candidate for next-generation high-density embedded non-volatile memory [1-2]. However, 1T1R STT-MRAM suffers from limited sensing margin and high write power. As shown in Fig. 30.2.1(a), sense amplifier design is challenging due to the small difference (only 2x) between the high-resistance state (RAP) and the low-resistance state (RP), as well as RAP degradation with increasing temperature. Moreover, RP and RAP resistance distributions shift with process variation, requiring a read reference (Vref) that tracks process. To improve the sensing margin, several offset-cancellation methods have been reported to reduce sense amplifier mismatch [3]. However, these methods use multiple capacitors and hence incur significant area overheads. To address this issue, we propose an offset-cancelled sense amplifier that uses only a single capacitor to significantly improve the sensing margin by more than 60%. A second design challenge for STT-MRAM stems from the high current needed to flip a cell during a write operation. For non-volatile memory applications with a 10-year retention time requirement, the write current can be as high as several hundred μA. However, as shown in Fig. 30.2.1(b), the required write time varies with the state change required (0→1 or 1→0), process variation, and temperature. As a result, a fixed write time that ensures successful write for all conditions wastes a significant energy for typical or average conditions. We propose an in situ write-self-termination method to reduce write energy in most scenarios. The sense amplifier is reconfigured to continuously monitor the write operation and automatically shuts off the write drivers when the state transition is detected, without an area or timing penalty. In addition, dual dummy columns are added in each array to provide read Vref tracking of row-wise PVT variation. A 1Mb STT-MRAM was fabricated in 28nm technology, and achieves a 2.8ns read-access time at 25°C and 3.6ns at 120°C, respectively. With in-situ self-write-termination the write power is reduced by 47% with a 20ns write-access time at 25°C and by 60% at 120°C.
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