Hybrid thermal aware reconfigurable 3D IC with dynamic power gating architecture

In this paper we propose an innovative 3D IC architecture that combines reconfigurable 2D structure with monolithic 3D. This new architecture not only resolves Power Distributive Network (PDN) design and thermal management issues of traditional 3D-IC, but also provides additional power control and programmable routing capability. It provides a cost effective way to integrate different modules together using stacked interposer structure. With power rails and signal paths that can be routed dynamically using reconfigurable peripheral switches, the new system is adjustable. Moreover, area saving is achieved by using monolithic 3D to realize the modules. With the corresponding new thermal aware hierarchical simulated annealing floorplan algorithm designed for our hybrid reconfigurable architecture, the thermal problem can be further alleviated. Our testing results on 15 benchmarks show that we obtain an average 1.69× lower temperature and average 2.82× smaller power compared with traditional 2D SoC structure, 1.3× lower temperature compared to traditional 3D structure.