缓冲电路的提出,以减少BJT因高估而崩溃的问题

Keerti Vyas, G. Jain, V. Maurya, A. Raman
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引用次数: 0

摘要

采用目视分析、x射线检查、电学检查和显微检查等方法,研究了两种电路中基极最大开路电压(vceo)、基极最大开路电压(vcbo)、基极最大短路电压(vces)和基极最大短路电压(vcbs)超过额定值时对晶体管性能的影响。这项研究有助于提高晶体管在现代电子设备中的可靠性。我们在此建议采用缓冲电路来减少上述问题。目视分析、电学检查和显微检查的结果以图片的形式显示。我们的建议可以在许多家用电器中实施,因为普通人通常不知道晶体管额定值的这一事实,因此可以防止由于不知道而导致的事故。
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Proposal of Snubber Circuit to Reduce Problem of Collapsing in BJT due to Overrating
The effect on transistors when maximum collector-emitter voltage under condition base is open (vceo), maximum collector-base voltage under condition emitter is open (vcbo), maximum collector-emitter voltage under condition base is shortened (vces) and maximum collector-base voltage under condition emitter is shortened (vcbs) ratings are got exceeded in two circuits are studied by visual analysis, x-ray examination, electrical examination and microscopic examination. This study helps in increasing the reliability of transistor used in all modern electronic equipments. We have proposed here for the implementation of snubber circuit to reduce the problem mentioned above. The results of visual analysis, electrical examination and microscopic examinations is shown in the form of pictures. Our proposal can be implemented in many house appliances, as common people are generally not aware of this fact of transistor ratings so the accidents due to unawareness can be prevented.
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