{"title":"基于级联码电流镜的低功耗、紧凑的物理不可克隆功能","authors":"Shibang Lin, Dejian Liang, Yuan Cao, Xiaofang Pan, Xiaojin Zhao","doi":"10.1109/APCCAS.2016.7803913","DOIUrl":null,"url":null,"abstract":"In this paper, we present a novel on-chip physical unclonable function (PUF) based on the cascode current mirrors. It exploits the process variation of a single transistor as the load of the current mirror to generate a reliable digital signature for the chip. By employing a cascode NMOS transistor in the current-mode PUF architecture, the proposed PUF greatly boosts the output impedance. As a result, the tiny mismatch current can be amplified to a large output voltage swing. In addition, the area overhead per bit is only two minimum-sized NMOS transistors: one for the load of the current mirror, the other one for the selecting switch. Moreover, the proposed PUF design is validated by our extensive post-layout simulation using UMC 65nm CMOS technology, with a power consumption per bit as low as 0.13μW. The average area for each response bit extracted from the design layout is 5.47μm2.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 1","pages":"127-130"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A low power and compact physical unclonable function based on the cascode current mirrors\",\"authors\":\"Shibang Lin, Dejian Liang, Yuan Cao, Xiaofang Pan, Xiaojin Zhao\",\"doi\":\"10.1109/APCCAS.2016.7803913\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a novel on-chip physical unclonable function (PUF) based on the cascode current mirrors. It exploits the process variation of a single transistor as the load of the current mirror to generate a reliable digital signature for the chip. By employing a cascode NMOS transistor in the current-mode PUF architecture, the proposed PUF greatly boosts the output impedance. As a result, the tiny mismatch current can be amplified to a large output voltage swing. In addition, the area overhead per bit is only two minimum-sized NMOS transistors: one for the load of the current mirror, the other one for the selecting switch. Moreover, the proposed PUF design is validated by our extensive post-layout simulation using UMC 65nm CMOS technology, with a power consumption per bit as low as 0.13μW. The average area for each response bit extracted from the design layout is 5.47μm2.\",\"PeriodicalId\":6495,\"journal\":{\"name\":\"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"13 1\",\"pages\":\"127-130\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2016.7803913\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7803913","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low power and compact physical unclonable function based on the cascode current mirrors
In this paper, we present a novel on-chip physical unclonable function (PUF) based on the cascode current mirrors. It exploits the process variation of a single transistor as the load of the current mirror to generate a reliable digital signature for the chip. By employing a cascode NMOS transistor in the current-mode PUF architecture, the proposed PUF greatly boosts the output impedance. As a result, the tiny mismatch current can be amplified to a large output voltage swing. In addition, the area overhead per bit is only two minimum-sized NMOS transistors: one for the load of the current mirror, the other one for the selecting switch. Moreover, the proposed PUF design is validated by our extensive post-layout simulation using UMC 65nm CMOS technology, with a power consumption per bit as low as 0.13μW. The average area for each response bit extracted from the design layout is 5.47μm2.