A high-speed CMOS op-amp design technique using negative Miller capacitance

A method is presented in this paper for the design of high speed CMOS operational amplifiers (op-amp). The op-amp consists of an operational transconductance amplifier (OTA) followed by an output buffer. The OTA is compensated with a capacitor connected between the input and output of the buffer. An op-amp is designed in a 0.18 /spl mu/m standard digital CMOS technology and exhibits 86 dB DC gain. The unity gain frequency and phase margin are 392 MHz and 73/spl deg/, respectively, for a parallel combination of 2 pF and 1 k/spl Omega/ load. As compared to the conventional approach, the proposed compensation method results in a 1.5 times increase in unity gain frequency and a 35/spl deg/ improvement in the phase margin under the same load conditions.