A maximum total leakage current estimation method

As transistor size continues to scale down, leakage power has become a critical issue of integrated circuit design. The maximum total leakage current, which is mainly determined by the sum of subthreshold, gate and reverse biased junction BTBT leakage current, is an important parameter to guide low-leakage and high-performance circuit designs. Up to now, how to estimate the maximum leakage current accurately within endurable time remains unsolved. Precise simulators can calculate leakage current accurately, but are only practical for small circuits. In this paper, a fast maximum leakage current estimation method is introduced accompanied with our gate-level leakage current simulator called iLeakage. Experiments on ISCAS circuit suits show that the simulator is significantly accelerated under acceptable error compared with HSPICE and the algorithm is applicable for large circuits.