Method of the accelerated verification of ECC (Error — Correcting codes) codecs by means of Simulink/Matlab packet

Nowadays there are a lot of software packets for simulation, modeling, debugging of hardware module description. However there are some issues related with functional testing of the algebraic blocks and algorithms. In case of comparison the designed algorithm with reference one we need a wide library of well-known proven models. MatLab packet has the large library of many famous algorithm models rather than other simulators. Another approach is to design own testbenches with proven software algorithm implementation, but sometimes it can be very difficult. This article describes a method of statistic analysis during the error-correcting codes decoding by the codecs with designed hardware by means Simulink/Matlab library elements and its interaction with SAD (System of automatic design) for hardware simulation. For accelerating the offered approach it is supposed the cross-platform modeling using evaluation board with FPGA. This method decreases in order statistic analysis time of error-correcting capability compared with this analysis by means of PC only. Also the model of non-binary symbol noise for Reed-Solomon codecs is proposed.