{"title":"基于二维代数整数编码的低功耗DCT IP核","authors":"Minyi Fu, G. Jullien, V. Dimitrov, M. Ahmadi","doi":"10.1109/ISCAS.2004.1329384","DOIUrl":null,"url":null,"abstract":"This paper discusses the application of a new two dimensional algebraic integer encoding scheme for the design of a DCT processor core for JPEG and MPEG applications. The paper concentrates on the efficient implementation of a 2D algebraic integer encoding procedure. The processor takes advantage of the low complexity, multiplierless, high-precision nature of the algebraic integer encoding scheme to achieve low power consumption. Test results from a proof-of-concept 0.18 /spl mu/m CMOS 8/spl times/8 DCT chip demonstrate a low power dissipation of 7.5 mW at 75 MHz.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"58 1","pages":"II-765"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":"{\"title\":\"A low-power DCT IP core based on 2D algebraic integer encoding\",\"authors\":\"Minyi Fu, G. Jullien, V. Dimitrov, M. Ahmadi\",\"doi\":\"10.1109/ISCAS.2004.1329384\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses the application of a new two dimensional algebraic integer encoding scheme for the design of a DCT processor core for JPEG and MPEG applications. The paper concentrates on the efficient implementation of a 2D algebraic integer encoding procedure. The processor takes advantage of the low complexity, multiplierless, high-precision nature of the algebraic integer encoding scheme to achieve low power consumption. Test results from a proof-of-concept 0.18 /spl mu/m CMOS 8/spl times/8 DCT chip demonstrate a low power dissipation of 7.5 mW at 75 MHz.\",\"PeriodicalId\":6445,\"journal\":{\"name\":\"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)\",\"volume\":\"58 1\",\"pages\":\"II-765\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"27\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2004.1329384\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2004.1329384","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-power DCT IP core based on 2D algebraic integer encoding
This paper discusses the application of a new two dimensional algebraic integer encoding scheme for the design of a DCT processor core for JPEG and MPEG applications. The paper concentrates on the efficient implementation of a 2D algebraic integer encoding procedure. The processor takes advantage of the low complexity, multiplierless, high-precision nature of the algebraic integer encoding scheme to achieve low power consumption. Test results from a proof-of-concept 0.18 /spl mu/m CMOS 8/spl times/8 DCT chip demonstrate a low power dissipation of 7.5 mW at 75 MHz.
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