Low power and highly reliable gates using arrays of optimally sized transistors

This paper introduces an enabling transistor sizing method for classical CMOS gates in advanced technology nodes through simple examples. The well-known CMOS inverter is used here both for presenting the different sizing options as well as for simulations for weighting performances. These preliminary results show that sizing is far from exhausting its potential as still allowing to: (i) improve delay and power; (ii) increase the static noise margins (SNMs); (iii) modify threshold voltages (VTH); and also (iv) reduce VTH variations (σVTH).