A Parallel Radix-2 k FFT Processor using Single-Port Merged-Bank Memory

This paper presents an area-efficient radix-2k FFT processor employing single-port memory, where the deployed memory is merged into 4 banks for arbitrary 2k-parallel computation. The proposed design enables the FFT input/output to operate in the parallelism equal to that of internal processing, and it paves the way for gaining high-throughput capability. Moreover, the in-place data caching strategy is available to allow the overlap between caching input data and supplying FFT results, which can further enhance throughput without consuming additional area. Theoretical and experimental comparisons demonstrate the proposed FFT processor can surpass the published related work in throughput while preserving high area efficiency.