Scaling Cu Pillars to 20um Pitch and Below: Critical Role of Surface Finish and Barrier Layers

High-performance computing has been aggressively driving pitch and performance requirements for off-chip interconnections over the last several decades, pushing solder-based interconnections to their limits. The most leading-edge Cu pillar technology faces many fundamental challenges in scaling to pitches below 30um, in particular with stress management and increased risks of Au embrittlement as solder volume is reduced All-intermetallic interconnections formed by solid-liquid interdiffusion (SLID) bonding have been concurrently explored to extend solders to finer pitches and improve their performance, but face their own set of manufacturability and reliability challenges that have, so far, limited their use to 3D-ICs. This research comprehensively addresses these challenges with innovative interconnection designs and advances in surface finish metallurgies, which allow for precisely controlled and unique interfacial reactions. A two-fold approach is pursued to: 1) extend scalability of conventional Cu pillars by replacing standard ENEPIG with ultra-thin electroless Pd autocatalytic Au (EPAG) surface finish, and, for further pitch scaling and enhanced electrical and thermal performances, 2) enable void-free, manufacturable all-intermetallic joints solely composed of the metastable Cu6Sn5 phase by introduction of diffusion barrier layers. This paper presents the design, demonstration and characterization of such high-performance solder-based interconnections at 20um pitch, highlighting the strategic role of surface finish and diffusion barrier layers for potential further pitch scaling.