The method of reducing the CMOS inverter switching energy

In CMOS inverters, the main part of the power supply is spent on charging the parasitic capacitance of the transistor gates and the load capacitance. Associated with this portion of energy is dynamic power consumption, which has two components—transient power consumption and capacitive-load power consumption. When the logic states of the inverter change in a short period of time, when the PMOS and NMOS transistors are switched simultaneously, a short-circuit current flows. Power losses from short-circuit current are only a small part of dynamic power consumption. For this reason, more attention is paid to reducing transient power consumption and capacitive-load power consumption. However, with the reduction in the size of the inverter transistors and the lowering of their threshold voltage, the short-circuit power losses must also be taken into account. Also, when the size of inverter transistors increases in powerful output buffers, the short-circuit current increases, which, in addition to increasing short-circuit power losses, can cause errors in the output logic. Therefore, the purpose of this work is to reduce short-circuit current and dynamic power consumption of the CMOS inverter. For this purpose, it is proposed to limit the short-circuit current by changing the state of additional PMOS and NMOS transistors included in the path of the short-circuit current. The state of additional transistors is changed by an additional clock signal with a special wave-form during the rising and falling edges of the main clock signal.