A 1 mV resolution 10 MS/s rail-to-rail comparator in 0.5 /spl mu/m low-voltage CMOS digital process

A new comparator architecture for high-resolution, rail-to-rail comparison at high-speed and low power dissipation is presented. The internal structure of the comparator permits one to overcome the technological constraints arising from a purely digital process. In particular, no precision capacitors are needed in this design. The newly developed circuit consists of three different gain stages before a dynamic latch. The first stage achieves a rail-to-rail operation owing to two distinct amplifiers working in parallel. The two outputs are separately offset compensated and then connected to a differential difference amplifier (DDA). A third high-swing stage, preceding a current-limited dynamic latch, is used to ensure a fast regeneration time. Particular care has been taken to limit not only the static, but also the dynamic power dissipation of the digital part. Circuit simulations on 0.5 /spl mu/m, 3.3 V single-supply CMOS digital technology show that this architecture can easily achieve a 10 MS/s speed, at the expense of only 165 /spl mu/A typical static current consumption.