Challenges in Chemical Mechanical Planarization defects of 7nm device and its improvement opportunities

CMP (Chemical Mechanical Planarization) defects are always one of the top yield detractors in IC (Integrated Circuit) devices since CMP processes have been applied in the semiconductor industry. Most of all, new structures and materials in 7nm devices make it challenging for CMP processes to meet device requirements. The CMP process obviously needs to control or contain not only the number of defects but also defect size in accordance with scaling speed. In this paper, the results of fundamental studies to elucidate CMP defects will be introduced and discussed as they pertain to 7nm devices. This paper will cover the phenomena and its research activities about atomic scale scratches, dishing control in uneven surface topography and surface defects with 7 nm logic device.