数字LDO中二元和多重一元加权功率级设计的比较分析

Fan Yang, Yasu Lu, P. Mok
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引用次数: 6

摘要

本文对新兴数字LDO的功率级设计进行了分析研究。讨论了两种广泛采用的分级方案,即二元和多重一元加权功率级分级。两种方法的目标都是实现数字LDO的速度和分辨率的平衡。二进制尺寸有利于大电流步进,然而,平均而言,可能会导致更振荡的电压沉降。多重一元尺寸通过逐步电压调节克服了这一点,如果选择更大的步长,速度会得到提高。本文还讨论了所需时钟频率的差异,以及功率级设计的建议。通过65纳米CMOS工艺的仿真进一步验证了这一对比分析。
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A comparative analysis on binary and multiple-unary weighted power stage design for digital LDO
An analytical study of designing power stage for the emerging digital LDO is presented in this paper. Two widely adopted sizing options are discussed, namely binary and multiple-unary weighted power stage sizing. Both methods target at realizing a balanced speed and resolution of the digital LDO. The binary sizing benefits the large current step, however, in average, may render a more oscillating voltage settling. The multiple unary sizing overcomes this by a step-by-step voltage regulation, and the speed is improved if a larger step size is selected. The difference of the required clock frequency, and suggestions in designing power stage are discussed in this paper as well. This comparative analysis is further verified by simulations in a 65-nm CMOS process.
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