A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS

The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all, by the need to achieve stringent bit error rates in the presence of interconnect constraints such as channel loss, impedance discontinuities induced by package and connectors, and crosstalk effects due to routing limitations in the package and on the motherboard. To effectively meet these challenges, the serial IO architecture has evolved to include more complex equalization schemes. Building on the previous work on a 4-tap DFE [1], this paper presents the design of a complete serial IO capable of operating up to 11.8Gb/s, and in particular, focuses on the integration of an adaptive equalizer and baud-rate CDR in the receiver of the serial IO.