A. Kennings, H. Mohammed, J. P. Skudlarek, Binghe Tian
{"title":"Cypress Delta39K/sup TM/。一个内存丰富，高性能，可扩展的CPLD架构","authors":"A. Kennings, H. Mohammed, J. P. Skudlarek, Binghe Tian","doi":"10.1109/CICC.2000.852634","DOIUrl":null,"url":null,"abstract":"The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the Warp/sup TM/ 6.0 software.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"24 1","pages":"135-138"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Cypress Delta39K/sup TM/. A memory-rich, high performance, scalable CPLD architecture\",\"authors\":\"A. Kennings, H. Mohammed, J. P. Skudlarek, Binghe Tian\",\"doi\":\"10.1109/CICC.2000.852634\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the Warp/sup TM/ 6.0 software.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"24 1\",\"pages\":\"135-138\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852634\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852634","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Cypress Delta39K/sup TM/. A memory-rich, high performance, scalable CPLD architecture
The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the Warp/sup TM/ 6.0 software.
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