一种0.18 /spl mu/m以上的高性能嵌入式DRAM的制造方法

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852618

T. Yoshida, H. Takato, T. Sakurai, K. Kokubun, K. Hiyama, A. Nomachi, Y. Takasu, M. Kishida, H. Ohtsuka, H. Naruse, Y. Morimasa, N. Yanagiya, T. Hashimoto, T. Noguchi, T. Miyamae, N. Iwabuchi, M. Tanaka, J. Kumagai, H. Ishiuchi

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引用次数: 2

摘要

提出了一种新的0.18 /spl mu/m代嵌入式DRAM的制造方法，实现了与Co salicide、双功函数门、小热预算和金属化等逻辑工艺的完全兼容，并引入了自对齐salicide Block (SSB)这一新的工艺技术。制造的嵌入式DRAM在保持时间和MOSFET AC/DC性能方面都表现出优异的特性，有望实现高性能的SOC(片上系统)应用。

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A fabrication method for high performance embedded DRAM of 0.18 /spl mu/m generation and beyond

A new fabrication method for embedded DRAM of 0.18 /spl mu/m generation is proposed, which realizes full compatibility with logic process such as Co salicide, dual work function gate, small thermal budget and metalization, and introduces Self-aligned Salicide Block (SSB), a new process technology. Fabricated embedded DRAM shows excellent characteristics with respect to both retention time and MOSFET AC/DC performance, promising high performance of SOC (System On a Chip) applications.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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