一种减少三维集成电路堆叠测试时间的测试存取机制

2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI:10.1109/APCCAS.2016.7804019

Inhyuk Choi, Hyunggoy Oh, Sungho Kang

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引用次数: 0

摘要

本文基于新兴的测试标准，设计了可重构测试存取机制(RTAM)，以减少三维集成电路(3d IC)的累积堆叠测试时间。RTAM使测试调度能够反映整个堆栈测试阶段中测试约束的变化。仿真结果表明，对于三维集成电路中的堆叠芯片，与不可重构TAM相比，RTAM可以减少累积堆叠测试时间。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Test access mechaism for stack test time reduction of 3-dimensional integrated circuit

In this paper, the reconfigurable test access mechanism (RTAM) is designed based on the emerging test standard to reduce the cumulative stack test time of the 3-dimensional integrated circuit (3-D IC). The RTAM enables the test scheduling to reflect the variation of the test constraints in the overall stack test phases. Simulation results show the RTAM achieves the cumulative stack test time reduction compared with a non-reconfigurable TAM for the stacked dies in the 3-D IC.

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2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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