C. Recoquillon, J. Bégueret, Y. Deval, G. Montignac, A. Baudry
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This paper presents the digitizer developed for the second phase of the ALMA (Atacama Large Millimeter Array) project. This ASIC is a monolithic A/D converter implemented in a BiCMOS 0.25 /spl mu/m. SiGe process from STMicroelectronics. The main features of the ADC are a 3 bit resolution (8 quantization levels), an input bandwidth from 2 to 4 GHz with 4 GHz sample rate. The design architecture of this digitizer is based on a conventional flash analog to digital converter structure. The comparator outputs are coded by a FDL encoder with a 3-bit Gray code. The measurement results, depicted at the end of this paper, show that the converter is operational for clock rates up to 5.5 GHz. The overall chip dissipates 1.4 W under 2.5 V and the die area is 9 mm/sup 2/.
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