An efficient architecture for a transputer based vehicle simulator

This paper presents an efficient architecture for the rendering and display sections of a vehicle simulator prototype. The architecture for the rendering stage, which consists of three independent concurrent units, has been optimised to support the two-layer dynamic load balancing technique. The display stage has also been partitioned to facilitate parallel updating of the pixel data to the dual frame buffers. The design of the frame buffers and the interface logic to access them by direct memory access (DMA) controllers (via three common address and data buses) and the colour video controller are also presented. Simulation results show that the adoption of DMA based memory transfer between the local memory of the transputer nodes and the frame buffers can alleviate the communication bottleneck prevalent in an earlier prototype.