电阻轮廓模型和电阻蚀刻模型在求解28nm金属电阻上损耗中的应用

Yiqun Tan, Weiwei Wu, Quan Chen, Shirui Yu
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引用次数: 1

摘要

当临界尺寸减小到28 nm及以上时,由于电阻损耗的增加而引起的蚀刻失败增加。传统的光学接近校正(OPC)模型只考虑二维(XY)轮廓,而忽略了垂直方向的扩散,导致抗蚀损失的估计不准确。严格的抗蚀剂模拟器可以模拟三维(3-D)抗蚀剂轮廓,但它们的速度不够快,无法在全芯片上进行校正或验证,这限制了它们在28nm节点以下技术开发中的应用。然而,一方面,正色调抗蚀剂的抗蚀损失主要是由光强度变化驱动的,而光强度变化是由OPC模型的光学部分精确建模的。另一方面,抗蚀损失可以通过工艺窗口条件下的快速收缩来反映。在本文中,我们证明了一个紧凑的电阻模型可以用来确定电阻损失,通过适当地选择光学成像平面进行校准或通过引入刻蚀后的CDs数据。这两种模型都可以用来识别全芯片上的上损耗热点。
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Application of resist profile model and resist-etch model in solving 28nm metal resist toploss
As critical dimensions decrease to 28 nm node and beyond, more etching failures are induced by the resist loss increases. Only two-dimensional (XY) contours are considered by traditional optical proximity correction (OPC) models, while vertical direction diffusion is neglected, resulting in inaccuracy in valuation of the resist loss. Rigorous resist simulators can simulate a three-dimensional (3-D) resist profile, but they are not fast enough for correction or verification on a full chip, which restrict their usage in technology development below 28nm node. However, for one hand, resist loss for positive-tone resists is mainly driven by optical intensity variations, which are accurately modeled by the optical portion of an OPC model. For the other, resist loss can be reflected by the quickly shrinking in process window condition. In this paper we show that a compact resist model can be used to determine resist loss by properly selecting the optical image plane for calibration or by introduction of CDs data after etching. Both these two models can be used to identify toploss hotspots on a full chip.
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