159mm2 32nm 32Gb MLC nand闪存,具有200MB/s异步DDR接口

Hyunggon Kim, Jungjune Park, Ki-Tae Park, Pansuk Kwak, O. Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyung Cho, Juseok Lee, Jungho Song, Soowoong Lee, H. Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, K. Kyung, Yong Lim, C. Chung
{"title":"159mm2 32nm 32Gb MLC nand闪存,具有200MB/s异步DDR接口","authors":"Hyunggon Kim, Jungjune Park, Ki-Tae Park, Pansuk Kwak, O. Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyung Cho, Juseok Lee, Jungho Song, Soowoong Lee, H. Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, K. Kyung, Yong Lim, C. Chung","doi":"10.1109/ISSCC.2010.5433912","DOIUrl":null,"url":null,"abstract":"Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in not only SSD but also conventional flash card system. The high speed interface in NAND flash, however, causes to increase chip size because of multiple memory planes more than two and additional signal buses [1]. Therefore, a high speed data interface capability with minimized chip size penalty is required in DDR NAND flash. This paper presents 159mm2 32Gb MLC NAND flash which is capable of 200MB/s read and 12MB/s write throughputs in a 32nm technology.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"8 1","pages":"442-443"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface\",\"authors\":\"Hyunggon Kim, Jungjune Park, Ki-Tae Park, Pansuk Kwak, O. Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyung Cho, Juseok Lee, Jungho Song, Soowoong Lee, H. Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, K. Kyung, Yong Lim, C. Chung\",\"doi\":\"10.1109/ISSCC.2010.5433912\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in not only SSD but also conventional flash card system. The high speed interface in NAND flash, however, causes to increase chip size because of multiple memory planes more than two and additional signal buses [1]. Therefore, a high speed data interface capability with minimized chip size penalty is required in DDR NAND flash. This paper presents 159mm2 32Gb MLC NAND flash which is capable of 200MB/s read and 12MB/s write throughputs in a 32nm technology.\",\"PeriodicalId\":6418,\"journal\":{\"name\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"volume\":\"8 1\",\"pages\":\"442-443\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2010.5433912\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2010.5433912","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21

摘要

通过器件缩放和多级单元提供低成本和高存储容量已成为NAND闪存发展的基本特征,以满足不断增长的闪存市场。然而,为了满足SSD (Solid-State Disk)应用等新兴市场对高读写吞吐量的需求,NAND闪存最近采用了DDR (Double Data Rate)等高速接口[1]。此外,随着NAND的进一步扩展,由于页面大小从2K增加到8K字节,甚至在双平面操作时增加到16K字节,整体NAND闪存性能中的一部分数据加载和数据输出时间已经增加。它不仅会严重影响SSD系统的整体性能,也会影响传统闪存卡系统的整体性能。然而,NAND闪存中的高速接口,由于多个存储平面超过两个和额外的信号总线,导致芯片尺寸增加[1]。因此,DDR NAND闪存需要具有最小芯片尺寸损失的高速数据接口能力。本文介绍了159mm2 32Gb MLC NAND闪存,该闪存在32nm技术下具有200MB/s的读取和12MB/s的写入吞吐量。
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A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface
Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in not only SSD but also conventional flash card system. The high speed interface in NAND flash, however, causes to increase chip size because of multiple memory planes more than two and additional signal buses [1]. Therefore, a high speed data interface capability with minimized chip size penalty is required in DDR NAND flash. This paper presents 159mm2 32Gb MLC NAND flash which is capable of 200MB/s read and 12MB/s write throughputs in a 32nm technology.
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