基于逻辑存储器的高速信号传输三维互连路由和堆叠策略评估

2012 IEEE 62nd Electronic Components and Technology Conference Pub Date : 2012-07-30 DOI:10.1109/ECTC.2012.6248798

J. Roullard, A. Farcy, S. Capraro, T. Lacrevaz, C. Bermond, G. Houzet, J. Charbonnier, C. Fuchs, C. Ferrandon, P. Leduc, B. Fléchet

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引用次数: 26

摘要

对三维堆叠技术进行了电学研究，以预测存储在逻辑应用中的高速数据传输。提取了存储器-处理器和处理器- bga通道的最大带宽频率，并对Face to Face和Face to Back 3D叠加以及中间体技术进行了比较。根据数据速率方面宽IO应用的预期电气规范，根据TSV密度执行的集成密度提出了路线图。

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Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic

3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.

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2012 IEEE 62nd Electronic Components and Technology Conference

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