Silicon field nanotransistor with a surroundung gate and a nonlinear geometry of the working area

A silicon CMOS nanotransistor with a cylindrical geometry with a fully enclosing gate with a non-linear geometry of the working area is discussed. Numerical studies of prototypes with a parabolic working area were performed using mathematical modeling using the software environment for instrumental technological modeling TCAD, based on the models of n- and p-type nanotransistors developed by TCAD. An inverter model has been developed for n- and p-type prototypes with an optimized radius ratio of 0.76. At control voltages of 0.6 V and a frequency of 25 GHz, the model predicts a maximum switching delay of 1.0 ps, an active power limit of 0.22 µW, and a static power of 72 pW. The electrophysical characteristics of the n-type prototype with dielectric stacks of gate oxide SiO2-Al2O3 and SiO2-HfO2 are analyzed numerically. The simulation results show that the use of high k stacks has a noticeable effect on key transistor characteristics. Thus, a parabolic nanotransistor architecture with an optimized radius ratio can potentially become a replacement for a cylindrical structure for high-speed low-voltage applications.