Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing

Defining the optimal clock-distribution network in VLSI is one of the most important aspects of high-speed SoC design. The existing design flows for clock tree network implementation are manual based and require long development cycle time. This long and iterative design flow is not optimized in terms of: clock-skew, insertion delay, clock signal rise/fall time, power dissipation, route resources, sensitivity to technology/design variations and time to market. This paper demonstrates a new approach which uses preliminary HSPICE simulations and dramatically improves the clock tree performance. This is done by smartly choosing the following parameters: number of driver levels, driver size, wire width/space and wire length between levels. These parameters are used as inputs to an automatic clock tree synthesis tool in order to get better results by the automatic synthesis tool. This approach is applied to a chip level clock tree network of the new Freescale Semiconductor MSC8122 Quad Core DSP (500 MHz, 90 nm CMOS technology, 0.9686 cm/spl times/1.1792 cm die size). This results in saving 12% power dissipation and 15% route area without performance decreasing compared to the manual based flow.