On-chip calibration technique for delay line based BIST jitter measurement

On-chip calibration technique for delay line based time-to-digital converters (TDC) used in jitter measurement built-in self-test (BIST). The proposed technique utilizes pulse width modulation (PWM) to generate accurate voltages to control delay elements within the TDC. Calibration is performed in three stages; accuracy fine-tuning, measurement dynamic range adjustment, and characteristic curve generation. Preliminary simulation results using the calibration technique on a modified Vernier delay line (VDL) BIST provided a cycle-to-cycle jitter resolution of /spl sim/5 ps. The calibration design consists of digital CMOS components and has a potential die area of 0.03/spl mu/m/sup 2/. Calibration time is less than 1.1ms and only a single external calibration input pin is required in addition to the existing BIST.