采用0.4-/spl mu/m CMOS技术，设计了一种用于NRZ数据的2.5 gb /s时钟恢复电路

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852690

S. Anand, B. Razavi

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引用次数: 1

摘要

本文介绍了一种采用两级环形振荡器和采样保持鉴相器的2.5 gb /s锁相时钟恢复电路。在0.4-/spl mu/m数字CMOS技术中制造，恢复时钟在长度为2/sup 7/-1的PRBS序列中显示10.8 ps的RMS抖动，同时从3.3 v电源消耗50 mW的功率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-/spl mu/m CMOS technology

This paper describes a 2.5-Gb/s phase-locked clock recovery circuit utilizing a two-stage ring oscillator and a sample-and-hold phase detector. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the recovered clock exhibits an RMS jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 while dissipating 50 mW of power from a 3.3-V supply.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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