Y. Yabe, T. Kimura, Y. Aimoto, H. Heiuchi, Y. Nakazawa, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, K. Koyama
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Control and synchronization scheme for parallel image processing RAM with 128 processor elements and 16-Mb DRAM
A newly developed parallel image processing RAM (PIP-RAM) integrates 128 processor elements and a 16-Mb DRAM on a single chip. The paper presents three novel circuit design techniques: a data path control and synchronization scheme between processors and memory; a refresh scheme which enables refresh operations in parallel with arithmetic-logical operations; and a special block redundancy scheme.
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