On the fixed-point error analysis and VLSI architecture for FS1016 CELP decoder

In this paper, the fixed-point accuracy analysis and VLSI architecture of FS1O16 CELP decoder are presented. The code excited linear predictive (CELP) coder is the most effective technique among various linear predictive coding methods for speech compression. Hence to design a low cost and low power CELP decoder chip for the portable systems and wireless digital communication environment becomes increasingly important. The decoder VLSI architecture can achieve (1) excellent accuracy results due to the accuracy studies for the finite word length, (2) power saving and high speed operations resulting from the combined advantages of pipeline, current processing for LSE's interpolating and cosine operation, (3) table size reducing by applying the memoryless realization for stochastic codebook and partial sums technique, and (4) specification satisfying the FS1016 CELP coder.