{"title":"112Gb/s双二进制PAM-4话单的低复杂度Bang-Bang PD设计","authors":"Jinwang Zhang, Fangxu Lv, Zhengbin Pang, Jianjun Shi, Zixiang Tang, Geng Zhang","doi":"10.1109/ICICM54364.2021.9660249","DOIUrl":null,"url":null,"abstract":"The Bang-Bang phase detector (PD) design scheme of duo-binary(DB) four-level pulse amplitude modulation (PAM4) clock data recovery (CDR) with 112 Gb/s is put forward. In order to solve the problem of high signal attenuation and high bit error rate (BER) of high-speed serial transceiver, DB PAM-4 is used instead of PAM-4 technology to reduce signal loss. Aiming at the problem of complex phase detection of DB PAM-4 CDR based on multilevel modulation, a low complexity DB PAM-4 PD based on waveform filtering technique is proposed. The CDR model is constructed in Candence virtuoso with a working rate of 112 Gb/s. When the input jitter is 0. 5UI, the maximum jitter after locking is 1.2ps.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2 1","pages":"351-356"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Low complexity Bang-Bang PD Design of 112Gb/s Duo-Binary PAM-4 CDR\",\"authors\":\"Jinwang Zhang, Fangxu Lv, Zhengbin Pang, Jianjun Shi, Zixiang Tang, Geng Zhang\",\"doi\":\"10.1109/ICICM54364.2021.9660249\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Bang-Bang phase detector (PD) design scheme of duo-binary(DB) four-level pulse amplitude modulation (PAM4) clock data recovery (CDR) with 112 Gb/s is put forward. In order to solve the problem of high signal attenuation and high bit error rate (BER) of high-speed serial transceiver, DB PAM-4 is used instead of PAM-4 technology to reduce signal loss. Aiming at the problem of complex phase detection of DB PAM-4 CDR based on multilevel modulation, a low complexity DB PAM-4 PD based on waveform filtering technique is proposed. The CDR model is constructed in Candence virtuoso with a working rate of 112 Gb/s. When the input jitter is 0. 5UI, the maximum jitter after locking is 1.2ps.\",\"PeriodicalId\":6693,\"journal\":{\"name\":\"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"2 1\",\"pages\":\"351-356\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICM54364.2021.9660249\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM54364.2021.9660249","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low complexity Bang-Bang PD Design of 112Gb/s Duo-Binary PAM-4 CDR
The Bang-Bang phase detector (PD) design scheme of duo-binary(DB) four-level pulse amplitude modulation (PAM4) clock data recovery (CDR) with 112 Gb/s is put forward. In order to solve the problem of high signal attenuation and high bit error rate (BER) of high-speed serial transceiver, DB PAM-4 is used instead of PAM-4 technology to reduce signal loss. Aiming at the problem of complex phase detection of DB PAM-4 CDR based on multilevel modulation, a low complexity DB PAM-4 PD based on waveform filtering technique is proposed. The CDR model is constructed in Candence virtuoso with a working rate of 112 Gb/s. When the input jitter is 0. 5UI, the maximum jitter after locking is 1.2ps.
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