Mixed. PTL/static logic synthesis using genetic algorithms for low-power applications

We present a new mixed pass-transistor logic (PTL) and static CMOS logic synthesis method based on a genetic search. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/CMOS logic gates using BDDs. The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay or power consumption or both in a 0.25 /spl mu/m CMOS process. The average area, power consumption, and power-delay product of ISCAS85 and MCNC91 benchmark circuits using the proposed method are 25%, 40%, and 45% better than their static counterparts, respectively.