Li Li, P. Su, J. Xue, M. Brillhart, J. Lau, P. Tzeng, C. K. Lee, C. Zhan, M. Dai, H. Chien, S. Wu
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An ASIC chip measured at 22 mm × 18 mm × 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm × 10 mm × 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing. The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. 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引用次数: 37
摘要
高性能网络交换机和路由器的带宽每一代增加2到10倍。这反过来又推动了为高性能网络系统设计的专用集成电路(asic)及其外部存储设备的带宽要求。提出了低功耗、高密度和高带宽的3D集成电路,以解决ASIC与外部存储器之间的带宽挑战。本文提出了一种新颖的3D集成电路架构,该架构包括具有通硅过孔(TSV)的硅中间层和硅中间层两侧的互连布线层。在硅中间层的顶部安装了尺寸为22 mm × 18 mm × 0.4 mm的ASIC芯片,在硅中间层的底部安装了两个尺寸为10 mm × 10 mm × 0.4 mm的较小的存储芯片,并通过微碰撞互连。开发了一种独特的双面芯片到芯片(C2C)连接工艺,使ASIC和存储器能够以真正的3D系统级封装(SiP)格式集成。这种3D集成电路架构将有助于克服目前由于光刻晶圆加工中使用的光栅尺寸而导致的硅中间层的尺寸限制。3D集成电路堆栈组装在具有传统焊料凸起的有机封装基板上。顶部ASIC芯片和底部存储芯片之间的通信是通过tsv和硅中间层的布线层进行的。三维集成电路堆栈的热学和热力学分析用于评估封装热性能,优化材料选择和封装可靠性。建模和实验表征结果都用于深入了解3D IC技术,以解决ASIC和内存带宽挑战,并为下一代高性能网络系统开发ASIC和内存集成的最佳实践。
Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration
The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm × 18 mm × 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm × 10 mm × 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing. The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.