用于中央局应用的CMOS ADSL编解码器

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-24 DOI:10.1109/CICC.2000.852672

P. Siniscalchi, Jeanne K. Pitz, R. Hester, S. M. DeSoto, Minsheng Wang, Sucheendran Sridharan, Robert L. Halbach, D. Richardson, W. Bright, M. Sarraj, J. Hellums, C. Betty, Glenn H. Westphal

{"title":"用于中央局应用的CMOS ADSL编解码器","authors":"P. Siniscalchi, Jeanne K. Pitz, R. Hester, S. M. DeSoto, Minsheng Wang, Sucheendran Sridharan, Robert L. Halbach, D. Richardson, W. Bright, M. Sarraj, J. Hellums, C. Betty, Glenn H. Westphal","doi":"10.1109/CICC.2000.852672","DOIUrl":null,"url":null,"abstract":"A CMOS central office codec that supports Full Rate and G.Lite ADSL applications is described. The transmit channel consists of application-dependent digital filters, a 14 bit, 8.832 MSample/s current steering DAC, a 1.104 MHz analog filter and a programmable attenuator. The receive channel contains -17.5 to 33.5 dB of programmable gain, a 138 kHz analog low-pass filter, a 14 bit, 2.208 MSample/s pipeline ADC and a digital low-pass filter. The IC occupies 55.2 mm/sup 2/ and dissipates 450 mW from a 3.3 V supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"228 1","pages":"303-306"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A CMOS ADSL codec for central office applications\",\"authors\":\"P. Siniscalchi, Jeanne K. Pitz, R. Hester, S. M. DeSoto, Minsheng Wang, Sucheendran Sridharan, Robert L. Halbach, D. Richardson, W. Bright, M. Sarraj, J. Hellums, C. Betty, Glenn H. Westphal\",\"doi\":\"10.1109/CICC.2000.852672\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS central office codec that supports Full Rate and G.Lite ADSL applications is described. The transmit channel consists of application-dependent digital filters, a 14 bit, 8.832 MSample/s current steering DAC, a 1.104 MHz analog filter and a programmable attenuator. The receive channel contains -17.5 to 33.5 dB of programmable gain, a 138 kHz analog low-pass filter, a 14 bit, 2.208 MSample/s pipeline ADC and a digital low-pass filter. The IC occupies 55.2 mm/sup 2/ and dissipates 450 mW from a 3.3 V supply.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"228 1\",\"pages\":\"303-306\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852672\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852672","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 16

摘要

描述了一种支持全速率和G.Lite ADSL应用的CMOS中央局编解码器。发射通道由应用相关数字滤波器、14位、8.832 MSample/s电流转向DAC、1.104 MHz模拟滤波器和可编程衰减器组成。接收通道包含-17.5至33.5 dB可编程增益，138 kHz模拟低通滤波器，14位，2.208 MSample/s流水线ADC和数字低通滤波器。该IC占用55.2 mm/sup 2/， 3.3 V电源功耗450mw。

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A CMOS ADSL codec for central office applications

A CMOS central office codec that supports Full Rate and G.Lite ADSL applications is described. The transmit channel consists of application-dependent digital filters, a 14 bit, 8.832 MSample/s current steering DAC, a 1.104 MHz analog filter and a programmable attenuator. The receive channel contains -17.5 to 33.5 dB of programmable gain, a 138 kHz analog low-pass filter, a 14 bit, 2.208 MSample/s pipeline ADC and a digital low-pass filter. The IC occupies 55.2 mm/sup 2/ and dissipates 450 mW from a 3.3 V supply.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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