基于混合进位选择的模2n-1加法器高效VLSI设计

Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014) Pub Date : 2007-11-21 DOI:10.1109/SIPS.2007.4387534

Su-Hon Lin, M. Sheu, K. Wang, Jun-Jie Zhu, Si-Ying Chen

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引用次数: 2

摘要

本研究提出了一种新的混合携带选择(HCS)方法，用于推导有效的模2n-1加法。其所得的加法器结构简单，对所有n个值都具有规则性，主要由改进进位预判加法器(MCLA)、进位预测单元和简单复用器(MUX)组成。对于基于180nm标准单元技术的VLSI实现，基于hcs的模2n-1加法器在AreaxTime (AT)性能上优于现有的最新解决方案。基于hcs的216-1模块加法器芯片的布局面积为25709 um2，时钟速率为518MHz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection

A novel Hybrid-Carry-Selection (HCS) approach used for deriving an efficient modulo 2n-1 addition is presented in this study. Its resulting adder architecture which is mainly built by modified carry look-ahead adder (MCLA), carry prediction unit and simple multiplexer (MUX) is simple and regular for all n values. For VLSI implementation based on 180nm standard-cell technology, the HCS-based modulo 2n-1 adder demonstrates the superiority in AreaxTime (AT) performance over those of the latest existing solutions. The layout area and clock rate for HCS-based 216-1 modular adder chip are 25709 um2 and 518MHz respectively.

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Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)

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