基于XGBoost的门级网络混合多级硬件木马检测平台

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IET Computers and Digital Techniques Pub Date : 2022-02-16 DOI:10.1049/cdt2.12040
Ying Zhang, Sen Li, Xin Chen, Jiaqi Yao, Zhiming Mao, Jizhong Yang, Yifeng Hua
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引用次数: 4

摘要

针对恶意第三方厂商在电路设计阶段植入硬件木马(Hardware Trojan, HT)的问题,本文提出了一种基于XGBoost算法的混合模式门级硬件木马检测平台。该检测平台由多级高温定位和基于高温检测的电路结构组成。在多级高温定位中,将电路的每条导线视为一个节点,分析节点的静态特性,结合动态检测进行高温定位。在模块化HT结构检测中提取电路的网络结构特征,目的是准确、快速地识别HT。混合模式高温感应检测平台可以有效满足高温感应定位或快速准确检测等多种检测需求。在Trust-Hub基准上的实验结果表明,多级定位精度可达94.0%,模块化HT结构检测精度可达100%。模块化HT结构检测在特征提取上的速度是多级HT定位的4倍左右。因此,对于具体的高温检测问题,多级定位和模块化高温结构检测可以分别或协同应用,证明了所提出的混合模式门级高温检测方案的实用性和有效性。
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Hybrid multi-level hardware Trojan detection platform for gate-level netlists based on XGBoost

Coping with the problem of malicious third-party vendors implanting Hardware Trojan (HT) in the circuit design stage, this paper proposes a hybrid-mode gate-level hardware Trojan detection platform based on the XGBoost algorithm. This detection platform is composed of multi-level HT localization and circuit structure based HT detection. Each wire of the circuit is regarded as a node in multi-level HT localization, and static characteristics of nodes are analysed, combining with dynamic detection to locate HT. The network structure features of the circuit are extracted in modular HT structure detection, aiming to identify HT accurately and rapidly. The hybrid-mode HT detection platform can efficiently meet various detection requirements, such as HT localization or rapid and accurate HT detection. The experiment results on Trust-Hub benchmark show that the multi-level localization can achieve 94.0% location accuracy, and the modular HT structure detection accuracy can achieve 100%. The modular HT structure detection is about four times as fast as the multi-level HT localization on feature extraction. Therefore, multi-level localization and modular HT structure detection can be respectively or cooperatively applied for specific HT detection issues, which proves that the proposed hybrid-mode gate-level HT detection scheme is practical and effective.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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