用于高频超声成像系统的可重构彩色多普勒DSP引擎

Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014) Pub Date : 2007-11-21 DOI:10.1109/SIPS.2007.4387542

T. Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, A. Wu

{"title":"用于高频超声成像系统的可重构彩色多普勒DSP引擎","authors":"T. Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, A. Wu","doi":"10.1109/SIPS.2007.4387542","DOIUrl":null,"url":null,"abstract":"A single-chip reconfigurable Color Doppler DSP engine is presented. It acts as the computation kernel of the high-frequency ultrasonic imaging system under development. The flexibility of the proposed DSP engine enables users to acquire sufficient information as needed, while the specificity of the hardware compared to general-purpose processors reduces cost and power consumption. This chip is implemented by TSMC 0.18 ¿m 1P6M CMOS technology. The die size is 2.94*2.94 mm2, and the power consumption is 184 mW when frame rate = 50, frame size = 512*256, and packet size = 8.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"109 1","pages":"187-192"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems\",\"authors\":\"T. Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, A. Wu\",\"doi\":\"10.1109/SIPS.2007.4387542\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-chip reconfigurable Color Doppler DSP engine is presented. It acts as the computation kernel of the high-frequency ultrasonic imaging system under development. The flexibility of the proposed DSP engine enables users to acquire sufficient information as needed, while the specificity of the hardware compared to general-purpose processors reduces cost and power consumption. This chip is implemented by TSMC 0.18 ¿m 1P6M CMOS technology. The die size is 2.94*2.94 mm2, and the power consumption is 184 mW when frame rate = 50, frame size = 512*256, and packet size = 8.\",\"PeriodicalId\":93225,\"journal\":{\"name\":\"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)\",\"volume\":\"109 1\",\"pages\":\"187-192\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2007.4387542\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2007.4387542","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

提出了一种单片可重构的彩色多普勒DSP引擎。它是正在开发的高频超声成像系统的计算核心。所提出的DSP引擎的灵活性使用户能够根据需要获取足够的信息，同时与通用处理器相比，硬件的特殊性降低了成本和功耗。该芯片采用台积电0.18¿m 1P6M CMOS技术实现。当帧率为50，帧大小为512*256，包大小为8时，芯片尺寸为2.94*2.94 mm2，功耗为184 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems

A single-chip reconfigurable Color Doppler DSP engine is presented. It acts as the computation kernel of the high-frequency ultrasonic imaging system under development. The flexibility of the proposed DSP engine enables users to acquire sufficient information as needed, while the specificity of the hardware compared to general-purpose processors reduces cost and power consumption. This chip is implemented by TSMC 0.18 ¿m 1P6M CMOS technology. The die size is 2.94*2.94 mm2, and the power consumption is 184 mW when frame rate = 50, frame size = 512*256, and packet size = 8.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)

自引率

0.00%

发文量