A low power 100 MHz all digital delay-locked loop

All digital DLL is designed for synchronization of high frequency VLSI system with low power consumption and small area. Two new design method features are presented. First, the operation is described by Verilog HDL and verified. Second, using the circuit level simulations and optimizations, low power consumption and high speed is achieved. The simulation results show that the power consumption is 3.2 mW at 100 MHz, 2.0 V supply voltage without driver buffers; the area is 0.1 mm/sup 2/ and the proposed DLL has no jitter.