VHDL simulation acceleration using specialized functions

We present a new approach to speeding up VHDL simulation. In this approach, the simulation code is generated with routines for unused VHDL features stripped off. The VHDL simulator optimized in this way runs faster when the design is described mostly with simple constructs and expressions. We prepare multiple functions for each task in the simulation process. Each function is pre-optimized for each possible case. When a design is compiled and the simulation code is generated, we select functions that best fit with the design. With this approach and with several other optimization techniques, we obtained about twofold speedup.