A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation

Digital Fractional-N PLLs allows easy cancellation of ΔΣ quantization noise and spurs [1], [2]. However, the actual results depend dramatically on the linearity of the time-to-digital converter (TDC). This paper presents a 3MHz bandwidth fractional-N synthesizer, which combines a 4ps TDC with digital linearization algorithm and a feedback phase interpolator with mismatch cancellation algorithm. In contrast to other TDC linearization approaches [3], this structure allows multiplier-free computations, fast and accurate spur cancellation, as well as digital post-cancellation of phase errors induced by the phase interpolator mismatches, avoiding more complex calibration loops [4].