一种新型的基于fpga的扩展卡尔曼滤波器用于恒开关频率异步电动机无速度传感器直接转矩控制

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IET Computers and Digital Techniques Pub Date : 2021-03-10 DOI:10.1049/cdt2.12011
Remzi Inan
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引用次数: 1

摘要

本研究提出了一种基于fpga的环内硬件(HIL)仿真器,用于异步电动机(IM)无速度传感器的基于恒开关频率控制器的直接转矩控制(CSFC-DTC),并采用了一种新颖的双输入降阶扩展卡尔曼滤波器(bi - roekf)。在Xilinx Virtex XC5VLX-110T ML506 FPGA板上实现包含IM闭环无速度传感器驱动系统的HIL仿真器时,采用了IEEE 754标准中的全精度单浮点数。在此无速度传感器IM驱动系统的HIL仿真中,利用文献中首次提出的新颖BI-ROEKF估计定子磁链、转子机械角速度、负载转矩、定子和转子电阻等定子静止轴分量。提出的BI-ROEKF是将两种不同IM模型的非线性和线性系统输入函数应用到单降阶扩展卡尔曼滤波(ROEKF)算法中。从而降低了EKF的阶数和计算量。在FPGA上实现了IM无速度传感器驱动系统的HIL仿真,利用手写VHDL的优势,得到了最优的逻辑设计,从而减少了采样时间,而采样时间直接影响到新型BI-ROEKF等基于模型的估计器的估计性能,进而影响到驱动系统的控制性能。利用无速度传感器CSFC-DTC IM驱动系统,在HIL仿真器中测试了新型BI-ROEKF在不同挑战性场景下的估计性能。从而测试了数字化仿真器的控制性能和实现性能。最后给出了所设计的基于bi - roekf的无速度传感器CSFC-DTC HIL仿真器的估计和控制性能结果以及各部分的执行时间。
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A novel FPGA-Based Bi input-reduced order extended Kalman filter for speed-sensorless direct torque control of induction motor with constant switching frequency controller

This study proposes an FPGA-based hardware in the loop (HIL) emulator for speed-sensorless of induction motor (IM) constant switching frequency controller-based direct torque control (CSFC-DTC) with a novel bi input-reduced order extended Kalman filter (BI-ROEKF). The full precision single floating point numbers in the IEEE 754 standard are used during the implementation of the HIL emulator which contains closed-loop speed-sensorless drive system of IM on the Xilinx Virtex XC5VLX-110T ML506 FPGA board. In this HIL emulator of speed-sensorless IM drive system, stator stationary axis components of stator flux, rotor mechanical angular speed, load torque, stator and rotor resistances are estimated with the novel BI-ROEKF which is proposed for the first time in the literature. The proposed BI-ROEKF is created by applying two different non-linear and linear system input functions obtained from two different IM models to the single reduced order extended Kalman filter (ROEKF) algorithm. Thus, the order and the computational burden of the EKF are reduced. The HIL emulator of the speed-sensorless drive system of IM is implemented on FPGA using the advantage of hand-written VHDL on getting an optimal logical design to reduce the sampling time which directly effects the estimation performance of the model-based estimator like the novel BI-ROEKF and hence the control performance of drive system. The estimation performance of the novel BI-ROEKF is tested with speed-sensorless CSFC-DTC IM drive system under different challenging scenarios in HIL emulator. Thus, the control and the implementation performances of digitalised emulator are tested. Finally, the estimation and control performance results and the execution time of the each part of the proposed HIL emulator of the speed-sensorless BI-ROEKF-based CSFC-DTC of the IM are presented.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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