{"title":"数据流计算机体系结构中循环机制的发展","authors":"Yury Shikunov, Yury Stepchenkov, D. Khilko","doi":"10.1109/EICONRUS.2018.8317362","DOIUrl":null,"url":null,"abstract":"This paper covers non-conventional recurrent data-flow architecture, its features, and implementation aspects. Recurrence — the main feature of the new architecture efficiently solves data redundancy problem, typical for data-flow architectures while increasing performance. Conventional recurrence implementation has an overhead of configuration operand insertion that provides required functional fields (tags). Functional capabilities expansion of the architecture mechanism implementing this feature resulted in further efficiency by eliminating said overhead in some instances. We cover enhancements implemented in multicore recurrent data-flow architecture, designed to increase the versatility of recurrent computational process utilization. We compare Viterbi algorithm implementations with and without enhancements.","PeriodicalId":6562,"journal":{"name":"2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","volume":"29 1","pages":"1413-1418"},"PeriodicalIF":0.0000,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Recurrent mechanism developments in the data-flow computer architecture\",\"authors\":\"Yury Shikunov, Yury Stepchenkov, D. Khilko\",\"doi\":\"10.1109/EICONRUS.2018.8317362\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper covers non-conventional recurrent data-flow architecture, its features, and implementation aspects. Recurrence — the main feature of the new architecture efficiently solves data redundancy problem, typical for data-flow architectures while increasing performance. Conventional recurrence implementation has an overhead of configuration operand insertion that provides required functional fields (tags). Functional capabilities expansion of the architecture mechanism implementing this feature resulted in further efficiency by eliminating said overhead in some instances. We cover enhancements implemented in multicore recurrent data-flow architecture, designed to increase the versatility of recurrent computational process utilization. We compare Viterbi algorithm implementations with and without enhancements.\",\"PeriodicalId\":6562,\"journal\":{\"name\":\"2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)\",\"volume\":\"29 1\",\"pages\":\"1413-1418\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EICONRUS.2018.8317362\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EICONRUS.2018.8317362","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Recurrent mechanism developments in the data-flow computer architecture
This paper covers non-conventional recurrent data-flow architecture, its features, and implementation aspects. Recurrence — the main feature of the new architecture efficiently solves data redundancy problem, typical for data-flow architectures while increasing performance. Conventional recurrence implementation has an overhead of configuration operand insertion that provides required functional fields (tags). Functional capabilities expansion of the architecture mechanism implementing this feature resulted in further efficiency by eliminating said overhead in some instances. We cover enhancements implemented in multicore recurrent data-flow architecture, designed to increase the versatility of recurrent computational process utilization. We compare Viterbi algorithm implementations with and without enhancements.