用于列并行CMOS图像传感器的低功耗计数器

2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI:10.1109/APCCAS.2016.7804028

Jong-Seok Kim, Jin-O. Yoon, B. Choi

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引用次数: 5

摘要

提出了一种用于柱并行CMOS图像传感器的低功耗计数器(LPC)。与传统计数器相比，LPCs可以将计数器中d触发器(DFF)的开关事件数量减少50%。在200 MHz时钟信号下的仿真结果表明，传统计数器功耗为55.7 μW, LPC功耗为27.9 μW。

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Low-power counter for column-parallel CMOS image sensors

A low-power counter (LPC) for column-parallel CMOS image sensors (CISs) is presented. The proposed LPCs can reduce the number of switching events of D-flip-flop (DFF) in the counter by 50% compared to the traditional counter. The simulation results with 200 MHz of clock signal show that the power consumption of the traditional counter is 55.7 μW, and the proposed LPC is 27.9 μW.

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2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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